As an example of an integrated semiconductor memory incorporated in an LSI, there is a non-volatile memory. The non-volatile memory is a device characterized in that the stored data is not lost even when the power of the LSI is turned off, and it has become an extremely important device for using the LSI in various applications.
As an example of the non-volatile memory of the semiconductor device, there are a so-called floating gate memory and a memory using an insulator (see the following Non-Patent Document 1). It is known that the insulator-type memory, in which insulators are laminated and electric charge is stored in the traps at the interface of the insulators and those in the insulators, is not required to form new conductive layers in comparison to the floating gate memory and thus the memory has a good matching with the process for the CMOS LSI.
However, in the conventional memory in which electric charge is stored in the insulators (insulator-type memory), it is required to maintain the sufficient charge holding characteristics while repeating the charge injection and emission. Therefore, it is difficult to realize such a memory. For its solution, the technique for rewriting the stored data by injecting the charge with a different polarity instead of emitting the charge has been proposed (see the following Patent Document 1).
In this structure, the polycrystalline silicon gate (memory gate) for performing the memory operation and the gate for selecting the cell (selection gate) are separately formed. In this memory cell structure, two transistors composed of the memory gate and fundamentally based on the n-channel MOS are arranged on both sides of the selection gate. The gate insulator of the memory gate has a so-called MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor (Silicon)) structure in which a silicon nitride film is sandwiched between two silicon oxide films. The gate insulator of the selection gate is composed of a silicon oxide film. The impurity diffusion layers (source, drain) are formed with using the selection gate and the memory gate as the masks.
Non-patent Document 1: pp. 496–506 in “Physics of Semiconductor Devices” second edition by S. Sze, published by Wiley-Interscience publication (USA) in 1981.
Patent Document 1: U.S. Pat. No. 5,969,383.